1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device.
2. Related Art
In recent years, memory elements have been rapidly becoming smaller in nonvolatile semiconductor memory devices such as EEPROMs (Electrically Erasable and Programmable Read Only Memories) in which writing and erasing can be electrically performed. In a case of an EEPROM, a high voltage is applied to the control gate electrode, so that electrons are injected into the floating gate electrode from the substrate side through a tunnel insulating film containing silicon (writing), or electrons are pulled out of the floating gate electrode (erasing) (see JP-A 08-125042 (KOKAI), for example). The floating gate electrode is located below the control gate electrode, with an interelectrode insulating film (also referred to as an interpoly insulating film) being interposed in between.
In such a case, a high voltage is required for injecting and pulling electrons into and out of the floating gate electrode, and large stress is caused in the tunnel insulating film. As a result, defects such as traps are formed in the tunnel insulating film, and the leakage current (stress-induced leakage current) increases and degrades the data retention characteristics and the likes.
The defects in the tunnel insulating film that cause the leakage current are formed, because a large amount of energy is generated due to the voltage application when the electrons in the silicon atoms tunnel through the conduction band of the tunnel insulating film to the cathode side. More specifically, when the tunneling electrons having the energy depending on the applied voltage move to the cathode side, impact ions are generated on the cathode side, and holes with a large amount of energy are generated or the hydrogen bonding existing in the silicon interfaces is cut off by the impact ions, resulting in the defects in the tunnel insulating film. The defects then cause leakage current and insulation breakdown.
To restrain the generation of defects in the tunnel insulating film, it is necessary to lower the voltage to be applied, or the write/erase voltage, and to reduce the energy of electrons to be injected. To effectively achieve those effects, the film thickness of the tunnel insulating film should be reduced. In a case where electrons form a FN (Fowler-Nordheim) tunneling current and pass through the tunnel insulating film, the amount of electrons injected J is generally expressed as:J==A×Eox2×exp(−B/Eox)
where A and B represent constants that are determined by the electron effective mass in the insulating film and the energy barrier, and Eox represents the electric field (=Vox/tox) to be induced in the tunnel insulating film. Accordingly, in a case where the tunnel insulating film having a film thickness tox of 8 nm is thinned to a 7-nm thick film, a decrease of approximately 12.5% is expected in the voltage required for injecting and pulling electrons into and out of the floating gate electrode. With this fact being taken into account, thinning the tunnel insulating film is effective in lowering the write/erase voltage (the program voltage).
Also, in a case where a high electric field is induced in the control gate electrode, and electrons are exchanged between the floating gate electrode and the substrate as in a NAND flash memory, a high electric field is induced in the interelectrode insulating film located between those electrodes. Where the devices are made smaller, the electric field to be induced into the interelectrode insulating film becomes larger, and causes a serious problem in reliability, unless the program voltage can be lowered. Therefore, it is necessary to lower the program voltage.
Meanwhile, it is known that the stress-induced leakage current increases, as the film thickness is made smaller. Although a thickness reduction can lower the voltage for erasing, the probability of electrons tunneling through the traps formed in the tunnel insulating film is increased by the thickness reduction. Therefore, the leakage current increases, despite a decrease in the number of defects. In this manner, the thickness reduction and the reliability are in a trade-off relationship, which is a significant cause of the hindrance to a decrease in film thickness of the tunnel oxide film.
As described above, there is the trade-off problem with a nonvolatile semiconductor memory device such as an EEPROM in which a reduction of the film thickness of the tunnel insulating film is effective in lowering the program voltage, but traps are formed when a high voltage is applied at the time of writing/erasing, resulting in an increase in leakage current. Therefore, a tunnel insulating film that restrains the stress-induced leakage current while lowering the program voltage has been demanded. However, it has been very difficult to satisfy such demand by conventional techniques.